job requirements:

1. Major in electronic information engineering or integrated circuit-related fields, with a bachelor's degree or above, and at least 3 years of experience in the full ASIC development process. Prior experience leading a complete tape-out project is preferred;  

2. Proficient in Verilog/SystemVerilog, and mastered the entire EDA tool flow, including RTL design, synthesis (DC), static timing analysis (STA), etc;  

3. Familiar with low-power design techniques (such as Power Gating, Multi-VDD), and possess experience in optimizing small-area circuits (such as gated clock reduction);  

4. Possess independent problem-solving skills and be capable of independently completing the closed-loop development from specification to mass production;  

5. Possess cross-departmental communication skills and be able to clearly convey design constraints to the team.

Job Responsibilities

1. Lead the definition of chip specifications, develop an architecture scheme that balances PPA (performance, power, area) according to scenario requirements, and output design constraint documents;  

2. Complete the micro-architecture design of key modules independently, and clarify the timing convergence path and low-power strategy;  

3. Write ETL code independently and complete functional simulation, address code coverage and assertion verification issues, and output verification reports;

4. Guide the layout design team to complete placement and routing, solve backend issues such as timing violations and crosstalk, and ensure that the chip area and yield meet standards;  

5. Collaborate with the verification team to optimize test cases and provide debugging support (such as root cause analysis of anomalies);

6. Lead the development of chip testing solutions (such as ATE machine debugging), analyze mass production failure cases, and iterate on design (such as ESD protection optimization);

7. Write technical specifications, DFT (Design for Testability) documents, and troubleshooting manuals, and establish a module-level IP reuse library.

Welfare

1. Salary is negotiable;  

2. Five-day workweek with 8 hours per day, and two-day weekend;  

3. Enjoy statutory holidays, annual leave, marriage leave, funeral leave, sick leave and other benefits in accordance with the law;  

4. Purchase of five insurances and one fund: including basic medical insurance (first-tier), endowment insurance, work-related injury insurance, unemployment insurance, maternity insurance, and housing provident fund;  

5. Regular salary adjustments once a year and the distribution of year-end bonuses;  

6. There is a monthly attendance bonus of 200 yuan;  

7. The company provides accommodation;  

8. Diverse extracurricular activities (afternoon tea, travel, team dinners, annual meetings, etc.); monthly birthday parties, afternoon tea, as well as badminton and table tennis activities, enriching employees' leisure time;  

9. The company provides a broad technical platform, a comprehensive training system, and a promotion mechanism;  

10. The working environment is beautiful, and the location is advantageous, being near a subway station and a bus stop.

Contact: Miss Xu

Phone: 0755-83190593

Email: xuyue@csc-ic.com

job requirements:

1. Electronics-related major, bachelor's degree or above, with over 3 years of technical job experience;

2. Possess experience as an FAE or R&D professional in chip OEMs, solution providers, or OEM manufacturers;

3. Proficient in capacitive touch principles and related project application debugging experience, with BLDC debugging experience;

4. Proficient in schematic design and 2-4 layer PCB layout, with expertise in operating various common electronic instruments;

5. Possess strong problem-solving and troubleshooting skills, capable of quickly responding to and resolving on-site issues;

6. Possess strong learning abilities, work enthusiasm, a positive attitude, and a strong sense of professional commitment;

7. Possess cross-departmental communication skills and the ability to clearly convey design constraints to the team.

fringe benefits:

1. Five days with eight-hour workdays, weekends off;

2. Enjoy statutory holidays, annual leave, marriage leave, bereavement leave, sick leave, and other benefits in accordance with the law;

3. Purchase social insurance and housing provident fund: including basic medical insurance (Tier 1), pension insurance, work-related injury insurance, unemployment insurance, maternity insurance, and housing provident fund;

4. Annual salary adjustments and year-end bonus distribution;

5. A monthly full attendance bonus of 200 yuan is provided;

6. The company provides accommodation;

7. Rich recreational activities (afternoon tea, travel, dining, annual meetings, etc.); Monthly birthday parties, afternoon tea sessions, as well as badminton and table tennis events, enriching employees' leisure lives;

8. The company offers a comprehensive technical platform, a well-established training system, and a robust promotion mechanism;

9. The working environment is pleasant, with a superior geographical location near subway stations and bus stops.

Contact: Miss Xu

Tel: 0755-83190593

Email: xuyue@csc-ic.com